%% ************ LibreSilicon's StdCellLibrary ******************* %% %% Organisation: Chipforge %% Germany / European Union %% %% Profile: Chipforge focus on fine System-on-Chip Cores in %% Verilog HDL Code which are easy understandable and %% adjustable. For further information see %% www.chipforge.org %% there are projects from small cores up to PCBs, too. %% %% File: StdCellLib/Documents/Book/chapter-sequential_stacked2.tex %% %% Purpose: Chapter Level File for Standard Cell Library Documentation %% %% ************ LaTeX with circdia.sty package *************** %% %% /////////////////////////////////////////////////////////////////// %% %% Copyright (c) 2018 - 2022 by %% chipforge %% All rights reserved. %% %% This Standard Cell Library is licensed under the Libre Silicon %% public license; you can redistribute it and/or modify it under %% the terms of the Libre Silicon public license as published by %% the Libre Silicon alliance, either version 1 of the License, or %% (at your option) any later version. %% %% This design is distributed in the hope that it will be useful, %% but WITHOUT ANY WARRANTY; without even the implied warranty of %% MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. %% See the Libre Silicon Public License for more details. %% %% /////////////////////////////////////////////////////////////////// \chapter{Two-stacked Sequential Cells} \input{section-LATN_latches} \input{section-LATP_latches} \input{section-DFFN_flipflops} \input{section-DFFP_flipflops}