This project is a hardware description built to demonstrate how to implement a fully functional RISC-V RV32I processor using a single-cycle architecture.
It serves as an educational reference and FPGA-ready design and showcases how to:
- 🚀 Execute RV32I base integer instructions in a single clock cycle
- ⚡ Interface with 7-segment displays via memory-mapped I/O
- 🔧 Implement modular CPU components (ALU, Control Unit, Registers, etc.)
- 🎨 Support branch and jump instructions with dedicated Branch Unit
- 📦 Load custom programs from hex files into instruction memory
- 🌍 Deploy to Intel/Altera FPGAs with Quartus Prime
| Feature | Description |
|---|---|
| RV32I Base Instructions | Supports R-type, I-type, S-type, B-type, U-type, and J-type instructions |
| Single-Cycle Design | Each instruction completes in exactly one clock cycle |
| Memory-Mapped I/O | 7-segment display imlemented via memory-mapped address |
| Modular Architecture | Each component (ALU, Control, Registers) is a separate testable module |
| FPGA Ready | Includes wrapper module for direct synthesis to Intel/Altera FPGAs |
| Simulation Support | Testbenches included for all modules with VCD waveform generation |
risc-v_single_cycle_processor/
├── ALU/ # Arithmetic Logic Unit
│ ├── ALU.sv # 32-bit ALU with 10 operations
│ └── ALU_tb.sv # ALU testbench
│
├── BranchUnit/ # Branch condition evaluation
│ ├── BranchUnit.sv # Evaluates BEQ, BNE, BLT, BGE, etc.
│ └── BranchUnit_tb.sv # Branch Unit testbench
│
├── ControlUnit/ # Instruction decoder
│ ├── ControlUnit.sv # Generates control signals from OpCode
│ └── ControlUnit_tb.sv # Control Unit testbench
│
├── DataMemory/ # Data RAM (8 KiB)
│ ├── DataMemory.sv # Supports LB, LH, LW, SB, SH, SW
│ └── DataMemory_tb.sv # Data Memory testbench
│
├── ImmGen/ # Immediate value generator
│ ├── ImmGen.sv # Sign-extends immediates for all formats
│ └── ImmGen_tb.sv # Immediate Generator testbench
│
├── InstructionMemory/ # Program ROM
│ ├── InstructionMemory.sv # Loads programs from .hex files
│ └── InstructionMemory_tb.sv # Instruction Memory testbench
│
├── ProgramCounter/ # PC register
│ ├── ProgramCounter.sv # 32-bit program counter with reset
│ └── ProgramCounter_tb.sv # Program Counter testbench
│
├── RegistersUnit/ # Register file (x0-x31)
│ ├── RegistersUnit.sv # 32 registers, dual read, single write
│ └── RegistersUnit_tb.sv # Registers Unit testbench
│
├── muxs/ # Multiplexers
│ ├── ALUA.sv # ALU input A selector (PC or rs1)
│ ├── ALUB.sv # ALU input B selector (rs2 or Imm)
│ ├── NextPC.sv # Next PC selector (PC+4 or ALURes)
│ └── RUDataWr.sv # Register write data selector
│
├── I_O_Implementation/ # FPGA I/O modules
│ ├── RiscV_SingleCycle_FPGA.sv # ⭐ Top module for FPGA synthesis
│ ├── RiscV_SingleCycle_FPGA_tb.sv # FPGA wrapper testbench
│ ├── test_display.sh # Script to test display modules (Linux)
│ ├── test_display.bat # Script to test display modules (Windows)
│ ├── SevenSegmentDisplay/ # 7-segment display drivers
│ │ ├── SevenSegmentDisplay.sv # Hex to 7-segment decoder
│ │ ├── DisplayController.sv # 8-display controller for 32-bit values
│ │ └── *_tb.sv # Testbenches for display modules
│ ├── 7_segments_test/ # Standalone 7-segment test project
│ │ ├── SevenSegTest.sv # Simple test for FPGA displays
│ │ ├── SevenSegTest.qpf/.qsf # Quartus project files
│ │ └── test_seven_seg.sh/.bat # Test scripts
│ └── programs/ # FPGA-specific programs
│ └── display_test.hex # Test program for 7-segment display
│
├── diagram/ # Architecture diagrams
│ └── risc-v_diagram.png # Processor block diagram
│
├── test_programs/ # Assembly programs in binary format
│ └── program.hex # Default test program
│
├── RiscV_SingleCycle.sv # Main processor module (simulation)
├── RiscV_SingleCycle_tb.sv # Top-level testbench
├── Risc-V_processor.qpf # Quartus project file
├── Risc-V_processor.qsf # Quartus settings file
├── run_test.sh # Script to run simulation (Linux)
└── run_test.bat # Script to run simulation (Windows)
| Type | Instructions |
|---|---|
| R-type | ADD, SUB, AND, OR, XOR, SLL, SRL, SRA, SLT, SLTU |
| I-type | ADDI, ANDI, ORI, XORI, SLTI, SLTIU, SLLI, SRLI, SRAI |
| Load | LB, LH, LW, LBU, LHU |
| Store | SB, SH, SW |
| Branch | BEQ, BNE, BLT, BGE, BLTU, BGEU |
| Jump | JAL, JALR |
| Upper | LUI, AUIPC |
- Icarus Verilog (iverilog) - For simulation
- GTKWave (optional) - For waveform visualization
- Intel Quartus Prime - For FPGA synthesis (optional)
-
Clone this repository
git clone https://github.com/MateoMor/risc-v_single_cycle_processor.git cd risc-v_single_cycle_processor -
Run the processor simulation
# Linux/macOS chmod +x run_test.sh ./run_test.sh # Windows run_test.bat
-
Test the 7-segment display modules
# Linux/macOS cd I_O_Implementation chmod +x test_display.sh ./test_display.sh # Windows cd I_O_Implementation test_display.bat
-
View waveforms (optional)
gtkwave riscv_tb.vcd
- Open Intel Quartus Prime
- Open the project file
Risc-V_processor.qpf - Set
I_O_Implementation/RiscV_SingleCycle_FPGA.svas the top-level entity - Assign pins according to your FPGA board (DE2-115, DE10-Lite, etc.)
- Compile and program the FPGA
Note: A standalone 7-segment test project is available in
I_O_Implementation/7_segments_test/for testing display functionality independently.
| Category | Technology |
|---|---|
| HDL | SystemVerilog (IEEE 1800-2012) |
| Simulator | Icarus Verilog |
| Waveform Viewer | GTKWave |
| FPGA Toolchain | Intel Quartus Prime |
| Target FPGAs | Intel Cyclone IV/V, MAX 10 |
| Address Range | Description |
|---|---|
0x00000000 - 0x00001FFF |
Data Memory (8 KiB) |
0xFFFFFFFC |
7-Segment Display (write-only) |
This project is designed to be reusable.
You can fork or clone it and adapt it to your own needs by:
- 🔧 Add new instructions: Extend
ControlUnit.svandALU.svfor M/F extensions - 🎨 Change I/O peripherals: Modify
RiscV_SingleCycle_FPGA.svfor LEDs, switches, UART - 🌍 Port to other FPGAs: Adjust pin assignments for Xilinx, Lattice, etc.
- ⚙️ Increase memory: Modify
DataMemory.svandInstructionMemory.svparameters
It works well as a starter boilerplate for computer architecture courses, FPGA learning, and RISC-V experimentation.
Source: "Arquitectura de Computadoras con RISC-V" by Jaramillo Villegas et al., Universidad Tecnológica de Pereira
Based on "Arquitectura de Computadoras con RISC-V" by Jaramillo Villegas et al., Universidad Tecnológica de Pereira.
For further reading, see the official publication: Arquitectura de Computadoras con RISC-V by Jaramillo Villegas et al., available through the Universidad Tecnológica de Pereira repository.
This project is licensed under the MIT License - see the LICENSE file for details.
© 2025 Mateo Morales