bootstrap: add bootstrap step to run stdarch-gen checks in CI by xonx4l · Pull Request #156674 · rust-lang/rust · GitHub

xonx4l · 2026-05-17T18:22:18Z

This PR ports stdarch-gen checks into the bootstrap test runner as a step, so that we can run the stdarch-gen checks via x.py test.

Changes -:
-> Adds a new StdarchGenCheck bootstrap step.
-> Mirrors https://github.com/rust-lang/stdarch/blob/f71ac102d30d5d1957277cbffc6ba631b67bffd1/.github/workflows/main.yml#L309-L333 (check-stdarch-gen job)
-> stdarch-gen-arm uses a nightly only feature (#![feature(pattern)]) but bootstrap's cargo runs on the beta toolchain thus we set RUSTC_BOOTSTRAP=1 on the child process so it builds.
-> The generators call out to rustfmt to format their output so rustfmt needs to be on PATH. So added bootstrap's rustfmt to PATH before each run. If rustfmt isn't available, the step fails early and tells the user to set rustfmt = true in bootstrap.toml .

r? @Kobzol

rustbot · 2026-05-17T18:22:24Z

Kobzol is not on the review rotation at the moment.
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rust-log-analyzer · 2026-05-18T07:57:53Z

The job aarch64-gnu-llvm-21-2 failed! Check out the build log: (web) (plain enhanced) (plain)

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//
// Instead, modify `crates/stdarch-gen-arm/spec/` and run the following command to re-generate this file:
//
// ```
// cargo run --bin=stdarch-gen-arm -- crates/stdarch-gen-arm/spec
// ```
#![allow(improper_ctypes)]

#[cfg(test)]
use stdarch_test::assert_instr;

use super::*;

#[doc = "CRC32 single round checksum for bytes (8 bits)."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32b)"]
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32b))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
)]
pub fn __crc32b(crc: u32, data: u8) -> u32 {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.crc32b"
        )]
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32b")]
        fn ___crc32b(crc: u32, data: u32) -> u32;
    }
    unsafe { ___crc32b(crc, data as u32) }
}
#[doc = "CRC32-C single round checksum for bytes (8 bits)."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cb)"]
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32cb))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
)]
pub fn __crc32cb(crc: u32, data: u8) -> u32 {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.crc32cb"
        )]
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cb")]
        fn ___crc32cb(crc: u32, data: u32) -> u32;
    }
    unsafe { ___crc32cb(crc, data as u32) }
}
#[doc = "CRC32-C single round checksum for quad words (64 bits)."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cd)"]
#[inline]
#[target_feature(enable = "crc")]
#[cfg(target_arch = "arm")]
#[cfg_attr(test, assert_instr(crc32cw))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
)]
pub fn __crc32cd(crc: u32, data: u64) -> u32 {
    let b: u32 = (data & 0xFFFFFFFF) as u32;
    let c: u32 = (data >> 32) as u32;
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
        fn ___crc32cw(crc: u32, data: u32) -> u32;
    }
    unsafe { ___crc32cw(___crc32cw(crc, b), c) }
}
#[doc = "CRC32-C single round checksum for bytes (16 bits)."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32ch)"]
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32ch))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
)]
pub fn __crc32ch(crc: u32, data: u16) -> u32 {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.crc32ch"
        )]
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32ch")]
        fn ___crc32ch(crc: u32, data: u32) -> u32;
    }
    unsafe { ___crc32ch(crc, data as u32) }
}
#[doc = "CRC32-C single round checksum for bytes (32 bits)."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32cw)"]
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32cw))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
)]
pub fn __crc32cw(crc: u32, data: u32) -> u32 {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.crc32cw"
        )]
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32cw")]
        fn ___crc32cw(crc: u32, data: u32) -> u32;
    }
    unsafe { ___crc32cw(crc, data) }
}
#[doc = "CRC32 single round checksum for quad words (64 bits)."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32d)"]
#[inline]
#[target_feature(enable = "crc")]
#[cfg(target_arch = "arm")]
#[cfg_attr(test, assert_instr(crc32w))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
)]
pub fn __crc32d(crc: u32, data: u64) -> u32 {
    let b: u32 = (data & 0xFFFFFFFF) as u32;
    let c: u32 = (data >> 32) as u32;
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
        fn ___crc32w(crc: u32, data: u32) -> u32;
    }
    unsafe { ___crc32w(___crc32w(crc, b), c) }
}
#[doc = "CRC32 single round checksum for bytes (16 bits)."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32h)"]
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32h))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
)]
pub fn __crc32h(crc: u32, data: u16) -> u32 {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.crc32h"
        )]
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32h")]
        fn ___crc32h(crc: u32, data: u32) -> u32;
    }
    unsafe { ___crc32h(crc, data as u32) }
}
#[doc = "CRC32 single round checksum for bytes (32 bits)."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/__crc32w)"]
#[inline]
#[target_feature(enable = "crc")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(test, assert_instr(crc32w))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_aarch32_crc32", issue = "125085")
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "stdarch_aarch64_crc32", since = "1.80.0")
)]
pub fn __crc32w(crc: u32, data: u32) -> u32 {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.crc32w"
        )]
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.crc32w")]
        fn ___crc32w(crc: u32, data: u32) -> u32;
    }
    unsafe { ___crc32w(crc, data) }
}
#[doc = "Signed Add and Accumulate Long Pairwise."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
fn priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i16.v8i8")]
        fn _priv_vpadal_s8(a: int16x4_t, b: int8x8_t) -> int16x4_t;
    }
    unsafe { _priv_vpadal_s8(a, b) }
}
#[doc = "Signed Add and Accumulate Long Pairwise."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s8"))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
fn priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v8i16.v16i8")]
        fn _priv_vpadalq_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t;
    }
    unsafe { _priv_vpadalq_s8(a, b) }
}
#[doc = "Signed Add and Accumulate Long Pairwise."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
fn priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i32.v4i16")]
        fn _priv_vpadal_s16(a: int32x2_t, b: int16x4_t) -> int32x2_t;
    }
    unsafe { _priv_vpadal_s16(a, b) }
}
#[doc = "Signed Add and Accumulate Long Pairwise."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s16"))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
fn priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v4i32.v8i16")]
        fn _priv_vpadalq_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t;
    }
    unsafe { _priv_vpadalq_s16(a, b) }
}
#[doc = "Signed Add and Accumulate Long Pairwise."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
fn priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v1i64.v2i32")]
        fn _priv_vpadal_s32(a: int64x1_t, b: int32x2_t) -> int64x1_t;
    }
    unsafe { _priv_vpadal_s32(a, b) }
}
#[doc = "Signed Add and Accumulate Long Pairwise."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.s32"))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
fn priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadals.v2i64.v4i32")]
        fn _priv_vpadalq_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t;
    }
    unsafe { _priv_vpadalq_s32(a, b) }
}
#[doc = "Signed Add and Accumulate Long Pairwise."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
fn priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i16.v8i8")]
        fn _priv_vpadal_u8(a: uint16x4_t, b: uint8x8_t) -> uint16x4_t;
    }
    unsafe { _priv_vpadal_u8(a, b) }
}
#[doc = "Signed Add and Accumulate Long Pairwise."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u8"))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
fn priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v8i16.v16i8")]
        fn _priv_vpadalq_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t;
    }
    unsafe { _priv_vpadalq_u8(a, b) }
}
#[doc = "Signed Add and Accumulate Long Pairwise."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
fn priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i32.v4i16")]
        fn _priv_vpadal_u16(a: uint32x2_t, b: uint16x4_t) -> uint32x2_t;
    }
    unsafe { _priv_vpadal_u16(a, b) }
}
#[doc = "Signed Add and Accumulate Long Pairwise."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u16"))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
fn priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v4i32.v8i16")]
        fn _priv_vpadalq_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t;
    }
    unsafe { _priv_vpadalq_u16(a, b) }
}
#[doc = "Signed Add and Accumulate Long Pairwise."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadal_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
fn priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v1i64.v2i32")]
        fn _priv_vpadal_u32(a: uint64x1_t, b: uint32x2_t) -> uint64x1_t;
    }
    unsafe { _priv_vpadal_u32(a, b) }
}
#[doc = "Signed Add and Accumulate Long Pairwise."]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/priv_vpadalq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg(target_arch = "arm")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vpadal.u32"))]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
fn priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadalu.v2i64.v4i32")]
        fn _priv_vpadalq_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t;
    }
    unsafe { _priv_vpadalq_u32(a, b) }
}
#[doc = "Absolute difference and accumulate (64-bit)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(saba)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vaba_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
    unsafe { simd_add(a, vabd_s16(b, c)) }
}
#[doc = "Absolute difference and accumulate (64-bit)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(saba)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vaba_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
    unsafe { simd_add(a, vabd_s32(b, c)) }
}
#[doc = "Absolute difference and accumulate (64-bit)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.s8"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(saba)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vaba_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
    unsafe { simd_add(a, vabd_s8(b, c)) }
}
#[doc = "Absolute difference and accumulate (64-bit)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vaba.u16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(uaba)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vaba_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t {
    unsafe { simd_add(a, vabd_u16(b, c)) }
---
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Extract vector from pair of vectors"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(ext, N = 15)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vextq_u8<const N: i32>(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
    static_assert_uimm_bits!(N, 4);
    unsafe {
        match N & 0b1111 {
            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
            1 => simd_shuffle!(
                a,
                b,
                [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
            ),
            2 => simd_shuffle!(
---
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Extract vector from pair of vectors"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(ext, N = 15)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vextq_p8<const N: i32>(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
    static_assert_uimm_bits!(N, 4);
    unsafe {
        match N & 0b1111 {
            0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]),
            1 => simd_shuffle!(
                a,
                b,
                [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
            ),
            2 => simd_shuffle!(
---
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f16)"]
#[inline]
#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmla)
)]
#[target_feature(enable = "neon,fp16")]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vfma_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
    unsafe { simd_fma(b, c, a) }
}
#[doc = "Floating-point fused Multiply-Add to accumulator (vector)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f16)"]
#[inline]
#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmla)
)]
#[target_feature(enable = "neon,fp16")]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vfmaq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
    unsafe { simd_fma(b, c, a) }
}
#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
    unsafe { simd_fma(b, c, a) }
}
#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
    unsafe { simd_fma(b, c, a) }
}
#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
    vfma_f32(a, b, vdup_n_f32_vfp4(c))
}
#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
    vfmaq_f32(a, b, vdupq_n_f32_vfp4(c))
}
#[doc = "Floating-point fused multiply-subtract from accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f16)"]
#[inline]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmls)
)]
#[target_feature(enable = "neon,fp16")]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vfms_f16(a: float16x4_t, b: float16x4_t, c: float16x4_t) -> float16x4_t {
    unsafe {
        let b: float16x4_t = simd_neg(b);
        vfma_f16(a, b, c)
    }
}
#[doc = "Floating-point fused multiply-subtract from accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f16)"]
#[inline]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmls)
)]
#[target_feature(enable = "neon,fp16")]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vfmsq_f16(a: float16x8_t, b: float16x8_t, c: float16x8_t) -> float16x8_t {
    unsafe {
        let b: float16x8_t = simd_neg(b);
        vfmaq_f16(a, b, c)
    }
}
#[doc = "Floating-point fused multiply-subtract from accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t {
    unsafe {
        let b: float32x2_t = simd_neg(b);
        vfma_f32(a, b, c)
    }
}
#[doc = "Floating-point fused multiply-subtract from accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t {
    unsafe {
        let b: float32x4_t = simd_neg(b);
        vfmaq_f32(a, b, c)
    }
}
#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
    vfms_f32(a, b, vdup_n_f32_vfp4(c))
}
#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
    vfmsq_f32(a, b, vdupq_n_f32_vfp4(c))
}
#[doc = "Duplicate vector element to vector"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(test, assert_instr(nop))]
pub fn vget_high_f16(a: float16x8_t) -> float16x4_t {
    unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
}
#[doc = "Duplicate vector element to vector"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_low_f16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(target_arch = "arm", target_feature(enable = "fp16"))]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "stdarch_neon_fp16", since = "1.94.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
#[cfg(not(target_arch = "arm64ec"))]
#[cfg_attr(test, assert_instr(nop))]
pub fn vget_low_f16(a: float16x8_t) -> float16x4_t {
    unsafe { simd_shuffle!(a, a, [0, 1, 2, 3]) }
}
#[doc = "Duplicate vector element to vector or scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(ext)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vget_high_f32(a: float32x4_t) -> float32x2_t {
    unsafe { simd_shuffle!(a, a, [2, 3]) }
}
#[doc = "Duplicate vector element to vector or scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(ext)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vget_high_p16(a: poly16x8_t) -> poly16x4_t {
    unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
}
#[doc = "Duplicate vector element to vector or scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_p8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(ext)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vget_high_p8(a: poly8x16_t) -> poly8x8_t {
    unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
}
#[doc = "Duplicate vector element to vector or scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(ext)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vget_high_s16(a: int16x8_t) -> int16x4_t {
    unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
}
#[doc = "Duplicate vector element to vector or scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(ext)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vget_high_s32(a: int32x4_t) -> int32x2_t {
    unsafe { simd_shuffle!(a, a, [2, 3]) }
}
#[doc = "Duplicate vector element to vector or scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(ext)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vget_high_s8(a: int8x16_t) -> int8x8_t {
    unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
}
#[doc = "Duplicate vector element to vector or scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(ext)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vget_high_u16(a: uint16x8_t) -> uint16x4_t {
    unsafe { simd_shuffle!(a, a, [4, 5, 6, 7]) }
}
#[doc = "Duplicate vector element to vector or scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(ext)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vget_high_u32(a: uint32x4_t) -> uint32x2_t {
    unsafe { simd_shuffle!(a, a, [2, 3]) }
}
#[doc = "Duplicate vector element to vector or scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_high_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmov"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(ext)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vget_high_u8(a: uint8x16_t) -> uint8x8_t {
    unsafe { simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]) }
---
            ),
        )
    }
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlaq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe {
        vmlaq_u16(
            a,
            b,
            simd_shuffle!(
---
            ),
        )
    }
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlaq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
    static_assert_uimm_bits!(LANE, 3);
    unsafe {
        vmlaq_s16(
            a,
            b,
            simd_shuffle!(
---
            ),
        )
    }
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlaq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
    static_assert_uimm_bits!(LANE, 3);
    unsafe {
        vmlaq_u16(
            a,
            b,
            simd_shuffle!(
---
            ),
        )
    }
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmla_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmla_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmla_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe { vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmla_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe { vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlaq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe {
        vmlaq_s32(
            a,
            b,
            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlaq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe {
        vmlaq_u32(
            a,
            b,
            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlaq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe {
        vmlaq_s32(
            a,
            b,
            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlaq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe {
        vmlaq_u32(
            a,
            b,
            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
    vmla_f32(a, b, vdup_n_f32(c))
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
    vmlaq_f32(a, b, vdupq_n_f32(c))
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
    vmla_s16(a, b, vdup_n_s16(c))
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
    vmlaq_s16(a, b, vdupq_n_s16(c))
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
    vmla_u16(a, b, vdup_n_u16(c))
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
    vmlaq_u16(a, b, vdupq_n_u16(c))
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
    vmla_s32(a, b, vdup_n_s32(c))
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
    vmlaq_s32(a, b, vdupq_n_s32(c))
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
    vmla_u32(a, b, vdup_n_u32(c))
}
#[doc = "Vector multiply accumulate with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
    vmlaq_u32(a, b, vdupq_n_u32(c))
}
#[doc = "Multiply-add to accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
    unsafe { simd_add(a, simd_mul(b, c)) }
}
#[doc = "Multiply-add to accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
    unsafe { simd_add(a, simd_mul(b, c)) }
}
#[doc = "Multiply-add to accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
    unsafe { simd_add(a, simd_mul(b, c)) }
}
#[doc = "Multiply-add to accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mla)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
---
            ),
        )
    }
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlsq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe {
        vmlsq_u16(
            a,
            b,
            simd_shuffle!(
---
            ),
        )
    }
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlsq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t {
    static_assert_uimm_bits!(LANE, 3);
    unsafe {
        vmlsq_s16(
            a,
            b,
            simd_shuffle!(
---
            ),
        )
    }
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlsq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t {
    static_assert_uimm_bits!(LANE, 3);
    unsafe {
        vmlsq_u16(
            a,
            b,
            simd_shuffle!(
---
            ),
        )
    }
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmls_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmls_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmls_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe { vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmls_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe { vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) }
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlsq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe {
        vmlsq_s32(
            a,
            b,
            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlsq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe {
        vmlsq_u32(
            a,
            b,
            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlsq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe {
        vmlsq_s32(
            a,
            b,
            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls, LANE = 1)
)]
#[rustc_legacy_const_generics(3)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlsq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe {
        vmlsq_u32(
            a,
            b,
            simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t {
    vmls_f32(a, b, vdup_n_f32(c))
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t {
    vmlsq_f32(a, b, vdupq_n_f32(c))
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t {
    vmls_s16(a, b, vdup_n_s16(c))
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t {
    vmlsq_s16(a, b, vdupq_n_s16(c))
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t {
    vmls_u16(a, b, vdup_n_u16(c))
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t {
    vmlsq_u16(a, b, vdupq_n_u16(c))
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t {
    vmls_s32(a, b, vdup_n_s32(c))
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t {
    vmlsq_s32(a, b, vdupq_n_s32(c))
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t {
    vmls_u32(a, b, vdup_n_u32(c))
}
#[doc = "Vector multiply subtract with scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t {
    vmlsq_u32(a, b, vdupq_n_u32(c))
}
#[doc = "Multiply-subtract from accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t {
    unsafe { simd_sub(a, simd_mul(b, c)) }
}
#[doc = "Multiply-subtract from accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t {
    unsafe { simd_sub(a, simd_mul(b, c)) }
}
#[doc = "Multiply-subtract from accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t {
    unsafe { simd_sub(a, simd_mul(b, c)) }
}
#[doc = "Multiply-subtract from accumulator"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mls)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
---
            ),
        )
    }
}
#[doc = "Floating-point multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmul, LANE = 0)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_lane_f32<const LANE: i32>(a: float32x2_t, b: float32x2_t) -> float32x2_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
}
#[doc = "Floating-point multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmul, LANE = 0)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_laneq_f32<const LANE: i32>(a: float32x2_t, b: float32x4_t) -> float32x2_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
}
#[doc = "Floating-point multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmul, LANE = 0)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_lane_f32<const LANE: i32>(a: float32x4_t, b: float32x2_t) -> float32x4_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Floating-point multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmul, LANE = 0)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_laneq_f32<const LANE: i32>(a: float32x4_t, b: float32x4_t) -> float32x4_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_lane_s16<const LANE: i32>(a: int16x4_t, b: int16x4_t) -> int16x4_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_lane_s16<const LANE: i32>(a: int16x8_t, b: int16x4_t) -> int16x8_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(
                b,
---
            ),
        )
    }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_lane_s32<const LANE: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_lane_s32<const LANE: i32>(a: int32x4_t, b: int32x2_t) -> int32x4_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_lane_u16<const LANE: i32>(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_lane_u16<const LANE: i32>(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(
                b,
---
            ),
        )
    }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_lane_u32<const LANE: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_lane_u32<const LANE: i32>(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t {
    static_assert_uimm_bits!(LANE, 1);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_laneq_s16<const LANE: i32>(a: int16x4_t, b: int16x8_t) -> int16x4_t {
    static_assert_uimm_bits!(LANE, 3);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_laneq_s16<const LANE: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
    static_assert_uimm_bits!(LANE, 3);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(
                b,
---
            ),
        )
    }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_laneq_s32<const LANE: i32>(a: int32x2_t, b: int32x4_t) -> int32x2_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_laneq_s32<const LANE: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_laneq_u16<const LANE: i32>(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t {
    static_assert_uimm_bits!(LANE, 3);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_laneq_u16<const LANE: i32>(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
    static_assert_uimm_bits!(LANE, 3);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(
                b,
---
            ),
        )
    }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_laneq_u32<const LANE: i32>(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe { simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul, LANE = 1)
)]
#[rustc_legacy_const_generics(2)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_laneq_u32<const LANE: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
    static_assert_uimm_bits!(LANE, 2);
    unsafe {
        simd_mul(
            a,
            simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]),
        )
    }
}
#[doc = "Vector multiply by scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f16)"]
#[inline]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmul)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vmul_n_f16(a: float16x4_t, b: f16) -> float16x4_t {
    unsafe { simd_mul(a, vdup_n_f16(b)) }
}
#[doc = "Vector multiply by scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f16)"]
#[inline]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmul)
)]
#[target_feature(enable = "neon,fp16")]
#[unstable(feature = "stdarch_neon_f16", issue = "136306")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vmulq_n_f16(a: float16x8_t, b: f16) -> float16x8_t {
    unsafe { simd_mul(a, vdupq_n_f16(b)) }
}
#[doc = "Vector multiply by scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t {
    unsafe { simd_mul(a, vdup_n_f32(b)) }
}
#[doc = "Vector multiply by scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(fmul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t {
    unsafe { simd_mul(a, vdupq_n_f32(b)) }
}
#[doc = "Vector multiply by scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t {
    unsafe { simd_mul(a, vdup_n_s16(b)) }
}
#[doc = "Vector multiply by scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t {
    unsafe { simd_mul(a, vdupq_n_s16(b)) }
}
#[doc = "Vector multiply by scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t {
    unsafe { simd_mul(a, vdup_n_s32(b)) }
}
#[doc = "Vector multiply by scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t {
    unsafe { simd_mul(a, vdupq_n_s32(b)) }
}
#[doc = "Vector multiply by scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t {
    unsafe { simd_mul(a, vdup_n_u16(b)) }
}
#[doc = "Vector multiply by scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t {
    unsafe { simd_mul(a, vdupq_n_u16(b)) }
}
#[doc = "Vector multiply by scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t {
    unsafe { simd_mul(a, vdup_n_u32(b)) }
}
#[doc = "Vector multiply by scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t {
    unsafe { simd_mul(a, vdupq_n_u32(b)) }
}
#[doc = "Polynomial multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(pmul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v8i8")]
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.pmul.v8i8"
        )]
        fn _vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t;
    }
    unsafe { _vmul_p8(a, b) }
}
#[doc = "Polynomial multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(pmul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v16i8")]
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.pmul.v16i8"
        )]
        fn _vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t;
    }
    unsafe { _vmulq_p8(a, b) }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
    unsafe { simd_mul(a, b) }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
    unsafe { simd_mul(a, b) }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
    unsafe { simd_mul(a, b) }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
    unsafe { simd_mul(a, b) }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
    unsafe { simd_mul(a, b) }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
    unsafe { simd_mul(a, b) }
}
#[doc = "Multiply"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))]
#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))]
#[cfg_attr(
    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
    assert_instr(mul)
)]
#[cfg_attr(
    not(target_arch = "arm"),
    stable(feature = "neon_intrinsics", since = "1.59.0")
)]
#[cfg_attr(
    target_arch = "arm",
    unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
)]
pub fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
    unsafe { simd_mul(a, b) }
}
---
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_s16<const LANE1: i32, const LANE2: i32>(
    a: int16x8_t,
    b: int16x4_t,
) -> int16x8_t {
    static_assert_uimm_bits!(LANE1, 3);
    static_assert_uimm_bits!(LANE2, 2);
    unsafe {
        let b: int16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);
        match LANE1 & 0b111 {
            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_s32<const LANE1: i32, const LANE2: i32>(
    a: int32x4_t,
    b: int32x2_t,
) -> int32x4_t {
    static_assert_uimm_bits!(LANE1, 2);
    static_assert_uimm_bits!(LANE2, 1);
    unsafe {
        let b: int32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);
        match LANE1 & 0b11 {
            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_u8<const LANE1: i32, const LANE2: i32>(
    a: uint8x16_t,
    b: uint8x8_t,
) -> uint8x16_t {
    static_assert_uimm_bits!(LANE1, 4);
    static_assert_uimm_bits!(LANE2, 3);
    unsafe {
        let b: uint8x16_t =
            simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
        match LANE1 & 0b1111 {
            0 => simd_shuffle!(
                a,
                b,
                [
                    16 + LANE2 as u32,
                    1,
---
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_u16<const LANE1: i32, const LANE2: i32>(
    a: uint16x8_t,
    b: uint16x4_t,
) -> uint16x8_t {
    static_assert_uimm_bits!(LANE1, 3);
    static_assert_uimm_bits!(LANE2, 2);
    unsafe {
        let b: uint16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);
        match LANE1 & 0b111 {
            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_u32<const LANE1: i32, const LANE2: i32>(
    a: uint32x4_t,
    b: uint32x2_t,
) -> uint32x4_t {
    static_assert_uimm_bits!(LANE1, 2);
    static_assert_uimm_bits!(LANE2, 1);
    unsafe {
        let b: uint32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]);
        match LANE1 & 0b11 {
            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_p8<const LANE1: i32, const LANE2: i32>(
    a: poly8x16_t,
    b: poly8x8_t,
) -> poly8x16_t {
    static_assert_uimm_bits!(LANE1, 4);
    static_assert_uimm_bits!(LANE2, 3);
    unsafe {
        let b: poly8x16_t =
            simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]);
        match LANE1 & 0b1111 {
            0 => simd_shuffle!(
                a,
                b,
                [
                    16 + LANE2 as u32,
                    1,
---
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_lane_p16<const LANE1: i32, const LANE2: i32>(
    a: poly16x8_t,
    b: poly16x4_t,
) -> poly16x8_t {
    static_assert_uimm_bits!(LANE1, 3);
    static_assert_uimm_bits!(LANE2, 2);
    unsafe {
        let b: poly16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]);
        match LANE1 & 0b111 {
            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_f32<const LANE1: i32, const LANE2: i32>(
    a: float32x4_t,
    b: float32x4_t,
) -> float32x4_t {
    static_assert_uimm_bits!(LANE1, 2);
    static_assert_uimm_bits!(LANE2, 2);
    unsafe {
        match LANE1 & 0b11 {
            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_f64<const LANE1: i32, const LANE2: i32>(
    a: float64x2_t,
    b: float64x2_t,
) -> float64x2_t {
    static_assert_uimm_bits!(LANE1, 1);
    static_assert_uimm_bits!(LANE2, 1);
    unsafe {
        match LANE1 & 0b1 {
            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_s8<const LANE1: i32, const LANE2: i32>(
    a: int8x16_t,
    b: int8x16_t,
) -> int8x16_t {
    static_assert_uimm_bits!(LANE1, 4);
    static_assert_uimm_bits!(LANE2, 4);
    unsafe {
        match LANE1 & 0b1111 {
            0 => simd_shuffle!(
                a,
                b,
---
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_s16<const LANE1: i32, const LANE2: i32>(
    a: int16x8_t,
    b: int16x8_t,
) -> int16x8_t {
    static_assert_uimm_bits!(LANE1, 3);
    static_assert_uimm_bits!(LANE2, 3);
    unsafe {
        match LANE1 & 0b111 {
            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_s32<const LANE1: i32, const LANE2: i32>(
    a: int32x4_t,
    b: int32x4_t,
) -> int32x4_t {
    static_assert_uimm_bits!(LANE1, 2);
    static_assert_uimm_bits!(LANE2, 2);
    unsafe {
        match LANE1 & 0b11 {
            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_s64<const LANE1: i32, const LANE2: i32>(
    a: int64x2_t,
    b: int64x2_t,
) -> int64x2_t {
    static_assert_uimm_bits!(LANE1, 1);
    static_assert_uimm_bits!(LANE2, 1);
    unsafe {
        match LANE1 & 0b1 {
            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_u8<const LANE1: i32, const LANE2: i32>(
    a: uint8x16_t,
    b: uint8x16_t,
) -> uint8x16_t {
    static_assert_uimm_bits!(LANE1, 4);
    static_assert_uimm_bits!(LANE2, 4);
    unsafe {
        match LANE1 & 0b1111 {
            0 => simd_shuffle!(
                a,
                b,
---
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_u16<const LANE1: i32, const LANE2: i32>(
    a: uint16x8_t,
    b: uint16x8_t,
) -> uint16x8_t {
    static_assert_uimm_bits!(LANE1, 3);
    static_assert_uimm_bits!(LANE2, 3);
    unsafe {
        match LANE1 & 0b111 {
            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_u32<const LANE1: i32, const LANE2: i32>(
    a: uint32x4_t,
    b: uint32x4_t,
) -> uint32x4_t {
    static_assert_uimm_bits!(LANE1, 2);
    static_assert_uimm_bits!(LANE2, 2);
    unsafe {
        match LANE1 & 0b11 {
            0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]),
            1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]),
            2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]),
            3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_u64<const LANE1: i32, const LANE2: i32>(
    a: uint64x2_t,
    b: uint64x2_t,
) -> uint64x2_t {
    static_assert_uimm_bits!(LANE1, 1);
    static_assert_uimm_bits!(LANE2, 1);
    unsafe {
        match LANE1 & 0b1 {
            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_p8<const LANE1: i32, const LANE2: i32>(
    a: poly8x16_t,
    b: poly8x16_t,
) -> poly8x16_t {
    static_assert_uimm_bits!(LANE1, 4);
    static_assert_uimm_bits!(LANE2, 4);
    unsafe {
        match LANE1 & 0b1111 {
            0 => simd_shuffle!(
                a,
                b,
---
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_p16<const LANE1: i32, const LANE2: i32>(
    a: poly16x8_t,
    b: poly16x8_t,
) -> poly16x8_t {
    static_assert_uimm_bits!(LANE1, 3);
    static_assert_uimm_bits!(LANE2, 3);
    unsafe {
        match LANE1 & 0b111 {
            0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]),
            1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]),
            2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]),
            3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]),
            4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]),
            5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]),
            6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]),
            7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 0))]
#[rustc_legacy_const_generics(1, 3)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcopyq_laneq_p64<const LANE1: i32, const LANE2: i32>(
    a: poly64x2_t,
    b: poly64x2_t,
) -> poly64x2_t {
    static_assert_uimm_bits!(LANE1, 1);
    static_assert_uimm_bits!(LANE2, 1);
    unsafe {
        match LANE1 & 0b1 {
            0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]),
            1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]),
            _ => unreachable_unchecked(),
        }
    }
}
#[doc = "Insert vector element from another vector element"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(nop))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcreate_f64(a: u64) -> float64x1_t {
    unsafe { transmute(a) }
}
#[doc = "Floating-point convert"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtn))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t {
    unsafe { simd_cast(a) }
}
#[doc = "Floating-point convert to higher precision long"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtl))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t {
    unsafe { simd_cast(a) }
}
#[doc = "Fixed-point convert to floating-point"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(scvtf))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t {
    unsafe { simd_cast(a) }
}
#[doc = "Fixed-point convert to floating-point"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(scvtf))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t {
    unsafe { simd_cast(a) }
}
#[doc = "Fixed-point convert to floating-point"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_u64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(ucvtf))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t {
    unsafe { simd_cast(a) }
}
#[doc = "Fixed-point convert to floating-point"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_u64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(ucvtf))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t {
    unsafe { simd_cast(a) }
}
#[doc = "Floating-point convert to lower precision"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f16_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtn2))]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vcvt_high_f16_f32(a: float16x4_t, b: float32x4_t) -> float16x8_t {
    vcombine_f16(a, vcvt_f16_f32(b))
}
#[doc = "Floating-point convert to higher precision"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f16)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtl2))]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
    vcvt_f32_f16(vget_high_f16(a))
}
#[doc = "Floating-point convert to lower precision narrow"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtn2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
    unsafe { simd_shuffle!(a, simd_cast(b), [0, 1, 2, 3]) }
}
#[doc = "Floating-point convert to higher precision long"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtl2))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t {
    unsafe {
        let b: float32x2_t = simd_shuffle!(a, a, [2, 3]);
        simd_cast(b)
    }
}
#[doc = "Fixed-point convert to floating-point"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(scvtf, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_n_f64_s64<const N: i32>(a: int64x1_t) -> float64x1_t {
    static_assert!(N >= 1 && N <= 64);
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64"
        )]
        fn _vcvt_n_f64_s64(a: int64x1_t, n: i32) -> float64x1_t;
    }
    unsafe { _vcvt_n_f64_s64(a, N) }
}
#[doc = "Fixed-point convert to floating-point"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_s64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(scvtf, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvtq_n_f64_s64<const N: i32>(a: int64x2_t) -> float64x2_t {
    static_assert!(N >= 1 && N <= 64);
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64"
        )]
        fn _vcvtq_n_f64_s64(a: int64x2_t, n: i32) -> float64x2_t;
    }
    unsafe { _vcvtq_n_f64_s64(a, N) }
}
#[doc = "Fixed-point convert to floating-point"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_u64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_n_f64_u64<const N: i32>(a: uint64x1_t) -> float64x1_t {
    static_assert!(N >= 1 && N <= 64);
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64"
        )]
        fn _vcvt_n_f64_u64(a: uint64x1_t, n: i32) -> float64x1_t;
    }
    unsafe { _vcvt_n_f64_u64(a, N) }
}
#[doc = "Fixed-point convert to floating-point"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_u64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(ucvtf, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvtq_n_f64_u64<const N: i32>(a: uint64x2_t) -> float64x2_t {
    static_assert!(N >= 1 && N <= 64);
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64"
        )]
        fn _vcvtq_n_f64_u64(a: uint64x2_t, n: i32) -> float64x2_t;
    }
    unsafe { _vcvtq_n_f64_u64(a, N) }
}
#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s64_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_n_s64_f64<const N: i32>(a: float64x1_t) -> int64x1_t {
    static_assert!(N >= 1 && N <= 64);
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64"
        )]
        fn _vcvt_n_s64_f64(a: float64x1_t, n: i32) -> int64x1_t;
    }
    unsafe { _vcvt_n_s64_f64(a, N) }
}
#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s64_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtzs, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvtq_n_s64_f64<const N: i32>(a: float64x2_t) -> int64x2_t {
    static_assert!(N >= 1 && N <= 64);
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64"
        )]
        fn _vcvtq_n_s64_f64(a: float64x2_t, n: i32) -> int64x2_t;
    }
    unsafe { _vcvtq_n_s64_f64(a, N) }
}
#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u64_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_n_u64_f64<const N: i32>(a: float64x1_t) -> uint64x1_t {
    static_assert!(N >= 1 && N <= 64);
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64"
        )]
        fn _vcvt_n_u64_f64(a: float64x1_t, n: i32) -> uint64x1_t;
    }
    unsafe { _vcvt_n_u64_f64(a, N) }
}
#[doc = "Floating-point convert to fixed-point, rounding toward zero"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u64_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtzu, N = 2))]
#[rustc_legacy_const_generics(1)]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvtq_n_u64_f64<const N: i32>(a: float64x2_t) -> uint64x2_t {
    static_assert!(N >= 1 && N <= 64);
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64"
        )]
        fn _vcvtq_n_u64_f64(a: float64x2_t, n: i32) -> uint64x2_t;
    }
    unsafe { _vcvtq_n_u64_f64(a, N) }
}
#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s64_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtzs))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.fptosi.sat.v1i64.v1f64"
        )]
        fn _vcvt_s64_f64(a: float64x1_t) -> int64x1_t;
    }
    unsafe { _vcvt_s64_f64(a) }
}
#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s64_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtzs))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.fptosi.sat.v2i64.v2f64"
        )]
        fn _vcvtq_s64_f64(a: float64x2_t) -> int64x2_t;
    }
    unsafe { _vcvtq_s64_f64(a) }
}
#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u64_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtzu))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.fptoui.sat.v1i64.v1f64"
        )]
        fn _vcvt_u64_f64(a: float64x1_t) -> uint64x1_t;
    }
    unsafe { _vcvt_u64_f64(a) }
}
#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u64_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtzu))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.fptoui.sat.v2i64.v2f64"
        )]
        fn _vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t;
    }
    unsafe { _vcvtq_u64_f64(a) }
}
#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s16_f16)"]
#[inline]
#[cfg_attr(test, assert_instr(fcvtas))]
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vcvta_s16_f16(a: float16x4_t) -> int16x4_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.fcvtas.v4i16.v4f16"
        )]
        fn _vcvta_s16_f16(a: float16x4_t) -> int16x4_t;
    }
    unsafe { _vcvta_s16_f16(a) }
}
#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s16_f16)"]
#[inline]
#[cfg_attr(test, assert_instr(fcvtas))]
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.fcvtas.v8i16.v8f16"
        )]
        fn _vcvtaq_s16_f16(a: float16x8_t) -> int16x8_t;
    }
    unsafe { _vcvtaq_s16_f16(a) }
}
#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s32_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtas))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.fcvtas.v2i32.v2f32"
        )]
        fn _vcvta_s32_f32(a: float32x2_t) -> int32x2_t;
    }
    unsafe { _vcvta_s32_f32(a) }
}
#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s32_f32)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtas))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.fcvtas.v4i32.v4f32"
        )]
        fn _vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t;
    }
    unsafe { _vcvtaq_s32_f32(a) }
}
#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s64_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtas))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.fcvtas.v1i64.v1f64"
        )]
        fn _vcvta_s64_f64(a: float64x1_t) -> int64x1_t;
    }
    unsafe { _vcvta_s64_f64(a) }
}
#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s64_f64)"]
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fcvtas))]
#[stable(feature = "neon_intrinsics", since = "1.59.0")]
pub fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.fcvtas.v2i64.v2f64"
        )]
        fn _vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t;
    }
    unsafe { _vcvtaq_s64_f64(a) }
}
#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u16_f16)"]
#[inline]
#[cfg_attr(test, assert_instr(fcvtau))]
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vcvta_u16_f16(a: float16x4_t) -> uint16x4_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.fcvtau.v4i16.v4f16"
        )]
        fn _vcvta_u16_f16(a: float16x4_t) -> uint16x4_t;
    }
    unsafe { _vcvta_u16_f16(a) }
}
#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u16_f16)"]
#[inline]
#[cfg_attr(test, assert_instr(fcvtau))]
#[target_feature(enable = "neon,fp16")]
#[stable(feature = "stdarch_neon_fp16", since = "1.94.0")]
#[cfg(not(target_arch = "arm64ec"))]
pub fn vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            any(target_arch = "aarch64", target_arch = "arm64ec"),
            link_name = "llvm.aarch64.neon.fcvtau.v8i16.v8f16"
        )]
        fn _vcvtaq_u16_f16(a: float16x8_t) -> uint16x8_t;
    }
    unsafe { _vcvtaq_u16_f16(a) }
}
#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u32_f32)"]
#[inline]
#[target_feature(enable = "neon")]
---
                13usize as i8,
                14usize as i8,
                15usize as i8,
            ),
            svdupq_n_s8(
                16usize as i8,
                17usize as i8,
                18usize as i8,
                19usize as i8,
                20usize as i8,
---
            ),
        ),
    );
}
#[simd_test(enable = "sve,f64mm")]
unsafe fn test_svld1ro_s16() {
    if svcntb() < 32 {
        println!("Skipping test_svld1ro_s16 due to SVE vector length");
        return;
    }
    svsetffr();
    let loaded = svld1ro_s16(svptrue_b16(), I16_DATA.as_ptr());
    assert_vector_matches_i16(
        loaded,
        svtrn1q_s16(
            svdupq_n_s16(
                0usize as i16,
                1usize as i16,
                2usize as i16,
                3usize as i16,
                4usize as i16,
                5usize as i16,
                6usize as i16,
                7usize as i16,
            ),
            svdupq_n_s16(
                8usize as i16,
                9usize as i16,
                10usize as i16,
                11usize as i16,
                12usize as i16,
                13usize as i16,
                14usize as i16,
                15usize as i16,
            ),
        ),
    );
}
#[simd_test(enable = "sve,f64mm")]
unsafe fn test_svld1ro_s32() {
    if svcntb() < 32 {
        println!("Skipping test_svld1ro_s32 due to SVE vector length");
        return;
    }
    svsetffr();
    let loaded = svld1ro_s32(svptrue_b32(), I32_DATA.as_ptr());
    assert_vector_matches_i32(
        loaded,
        svtrn1q_s32(
            svdupq_n_s32(0usize as i32, 1usize as i32, 2usize as i32, 3usize as i32),
            svdupq_n_s32(4usize as i32, 5usize as i32, 6usize as i32, 7usize as i32),
        ),
    );
}
#[simd_test(enable = "sve,f64mm")]
unsafe fn test_svld1ro_s64() {
    if svcntb() < 32 {
        println!("Skipping test_svld1ro_s64 due to SVE vector length");
        return;
    }
    svsetffr();
    let loaded = svld1ro_s64(svptrue_b64(), I64_DATA.as_ptr());
    assert_vector_matches_i64(
        loaded,
        svtrn1q_s64(
            svdupq_n_s64(0usize as i64, 1usize as i64),
            svdupq_n_s64(2usize as i64, 3usize as i64),
        ),
    );
}
#[simd_test(enable = "sve,f64mm")]
unsafe fn test_svld1ro_u8() {
    if svcntb() < 32 {
        println!("Skipping test_svld1ro_u8 due to SVE vector length");
        return;
    }
    svsetffr();
    let loaded = svld1ro_u8(svptrue_b8(), U8_DATA.as_ptr());
    assert_vector_matches_u8(
        loaded,
        svtrn1q_u8(
            svdupq_n_u8(
                0usize as u8,
                1usize as u8,
                2usize as u8,
                3usize as u8,
                4usize as u8,
---
                13usize as u8,
                14usize as u8,
                15usize as u8,
            ),
            svdupq_n_u8(
                16usize as u8,
                17usize as u8,
                18usize as u8,
                19usize as u8,
                20usize as u8,
---
            ),
        ),
    );
}
#[simd_test(enable = "sve,f64mm")]
unsafe fn test_svld1ro_u16() {
    if svcntb() < 32 {
        println!("Skipping test_svld1ro_u16 due to SVE vector length");
        return;
    }
    svsetffr();
    let loaded = svld1ro_u16(svptrue_b16(), U16_DATA.as_ptr());
    assert_vector_matches_u16(
        loaded,
        svtrn1q_u16(
            svdupq_n_u16(
                0usize as u16,
                1usize as u16,
                2usize as u16,
                3usize as u16,
                4usize as u16,
                5usize as u16,
                6usize as u16,
                7usize as u16,
            ),
            svdupq_n_u16(
                8usize as u16,
                9usize as u16,
                10usize as u16,
                11usize as u16,
                12usize as u16,
                13usize as u16,
                14usize as u16,
                15usize as u16,
            ),
        ),
    );
}
#[simd_test(enable = "sve,f64mm")]
unsafe fn test_svld1ro_u32() {
    if svcntb() < 32 {
        println!("Skipping test_svld1ro_u32 due to SVE vector length");
        return;
    }
    svsetffr();
    let loaded = svld1ro_u32(svptrue_b32(), U32_DATA.as_ptr());
    assert_vector_matches_u32(
        loaded,
        svtrn1q_u32(
            svdupq_n_u32(0usize as u32, 1usize as u32, 2usize as u32, 3usize as u32),
            svdupq_n_u32(4usize as u32, 5usize as u32, 6usize as u32, 7usize as u32),
        ),
    );
}
#[simd_test(enable = "sve,f64mm")]
unsafe fn test_svld1ro_u64() {
    if svcntb() < 32 {
        println!("Skipping test_svld1ro_u64 due to SVE vector length");
        return;
    }
    svsetffr();
    let loaded = svld1ro_u64(svptrue_b64(), U64_DATA.as_ptr());
    assert_vector_matches_u64(
        loaded,
        svtrn1q_u64(
            svdupq_n_u64(0usize as u64, 1usize as u64),
            svdupq_n_u64(2usize as u64, 3usize as u64),
        ),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1rq_f32() {
    svsetffr();
    let loaded = svld1rq_f32(svptrue_b32(), F32_DATA.as_ptr());
    assert_vector_matches_f32(
        loaded,
        svdupq_n_f32(0usize as f32, 1usize as f32, 2usize as f32, 3usize as f32),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1rq_f64() {
    svsetffr();
    let loaded = svld1rq_f64(svptrue_b64(), F64_DATA.as_ptr());
    assert_vector_matches_f64(loaded, svdupq_n_f64(0usize as f64, 1usize as f64));
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1rq_s8() {
    svsetffr();
    let loaded = svld1rq_s8(svptrue_b8(), I8_DATA.as_ptr());
    assert_vector_matches_i8(
        loaded,
        svdupq_n_s8(
            0usize as i8,
            1usize as i8,
            2usize as i8,
            3usize as i8,
            4usize as i8,
---
            15usize as i8,
        ),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1rq_s16() {
    svsetffr();
    let loaded = svld1rq_s16(svptrue_b16(), I16_DATA.as_ptr());
    assert_vector_matches_i16(
        loaded,
        svdupq_n_s16(
            0usize as i16,
            1usize as i16,
            2usize as i16,
            3usize as i16,
            4usize as i16,
            5usize as i16,
            6usize as i16,
            7usize as i16,
        ),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1rq_s32() {
    svsetffr();
    let loaded = svld1rq_s32(svptrue_b32(), I32_DATA.as_ptr());
    assert_vector_matches_i32(
        loaded,
        svdupq_n_s32(0usize as i32, 1usize as i32, 2usize as i32, 3usize as i32),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1rq_s64() {
    svsetffr();
    let loaded = svld1rq_s64(svptrue_b64(), I64_DATA.as_ptr());
    assert_vector_matches_i64(loaded, svdupq_n_s64(0usize as i64, 1usize as i64));
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1rq_u8() {
    svsetffr();
    let loaded = svld1rq_u8(svptrue_b8(), U8_DATA.as_ptr());
    assert_vector_matches_u8(
        loaded,
        svdupq_n_u8(
            0usize as u8,
            1usize as u8,
            2usize as u8,
            3usize as u8,
            4usize as u8,
---
            15usize as u8,
        ),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1rq_u16() {
    svsetffr();
    let loaded = svld1rq_u16(svptrue_b16(), U16_DATA.as_ptr());
    assert_vector_matches_u16(
        loaded,
        svdupq_n_u16(
            0usize as u16,
            1usize as u16,
            2usize as u16,
            3usize as u16,
            4usize as u16,
            5usize as u16,
            6usize as u16,
            7usize as u16,
        ),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1rq_u32() {
    svsetffr();
    let loaded = svld1rq_u32(svptrue_b32(), U32_DATA.as_ptr());
    assert_vector_matches_u32(
        loaded,
        svdupq_n_u32(0usize as u32, 1usize as u32, 2usize as u32, 3usize as u32),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1rq_u64() {
    svsetffr();
    let loaded = svld1rq_u64(svptrue_b64(), U64_DATA.as_ptr());
    assert_vector_matches_u64(loaded, svdupq_n_u64(0usize as u64, 1usize as u64));
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sb_gather_s32offset_s32_with_svst1b_scatter_s32offset_s32() {
    let mut storage = [0 as i8; 1280usize];
    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_s32(0, 1u32.try_into().unwrap());
    svst1b_scatter_s32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i8 || val == i as i8);
    }
    svsetffr();
    let loaded = svld1sb_gather_s32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
    assert_vector_matches_i32(
        loaded,
        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sh_gather_s32offset_s32_with_svst1h_scatter_s32offset_s32() {
    let mut storage = [0 as i16; 640usize];
    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_s32(0, 2u32.try_into().unwrap());
    svst1h_scatter_s32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i16 || val == i as i16);
    }
    svsetffr();
    let loaded =
        svld1sh_gather_s32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
    assert_vector_matches_i32(
        loaded,
        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sb_gather_s32offset_u32_with_svst1b_scatter_s32offset_u32() {
    let mut storage = [0 as u8; 1280usize];
    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_s32(0, 1u32.try_into().unwrap());
    svst1b_scatter_s32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as u8 || val == i as u8);
    }
    svsetffr();
    let loaded = svld1sb_gather_s32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
    assert_vector_matches_u32(
        loaded,
        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sh_gather_s32offset_u32_with_svst1h_scatter_s32offset_u32() {
    let mut storage = [0 as u16; 640usize];
    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_s32(0, 2u32.try_into().unwrap());
    svst1h_scatter_s32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as u16 || val == i as u16);
    }
    svsetffr();
    let loaded =
        svld1sh_gather_s32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
    assert_vector_matches_u32(
        loaded,
        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sb_gather_s64offset_s64_with_svst1b_scatter_s64offset_s64() {
    let mut storage = [0 as i8; 1280usize];
    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
    svst1b_scatter_s64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i8 || val == i as i8);
    }
    svsetffr();
    let loaded = svld1sb_gather_s64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
    assert_vector_matches_i64(
        loaded,
        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sh_gather_s64offset_s64_with_svst1h_scatter_s64offset_s64() {
    let mut storage = [0 as i16; 640usize];
    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
    svst1h_scatter_s64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i16 || val == i as i16);
    }
    svsetffr();
    let loaded =
        svld1sh_gather_s64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
    assert_vector_matches_i64(
        loaded,
        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sw_gather_s64offset_s64_with_svst1w_scatter_s64offset_s64() {
    let mut storage = [0 as i32; 320usize];
    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
    svst1w_scatter_s64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i32 || val == i as i32);
    }
    svsetffr();
    let loaded =
        svld1sw_gather_s64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
    assert_vector_matches_i64(
        loaded,
        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sb_gather_s64offset_u64_with_svst1b_scatter_s64offset_u64() {
    let mut storage = [0 as u8; 1280usize];
    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_s64(0, 1u32.try_into().unwrap());
    svst1b_scatter_s64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as u8 || val == i as u8);
    }
    svsetffr();
    let loaded = svld1sb_gather_s64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
    assert_vector_matches_u64(
        loaded,
        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sh_gather_s64offset_u64_with_svst1h_scatter_s64offset_u64() {
    let mut storage = [0 as u16; 640usize];
    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_s64(0, 2u32.try_into().unwrap());
    svst1h_scatter_s64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as u16 || val == i as u16);
    }
    svsetffr();
    let loaded =
        svld1sh_gather_s64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
    assert_vector_matches_u64(
        loaded,
        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sw_gather_s64offset_u64_with_svst1w_scatter_s64offset_u64() {
    let mut storage = [0 as u32; 320usize];
    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_s64(0, 4u32.try_into().unwrap());
    svst1w_scatter_s64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as u32 || val == i as u32);
    }
    svsetffr();
    let loaded =
        svld1sw_gather_s64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
    assert_vector_matches_u64(
        loaded,
        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sb_gather_u32offset_s32_with_svst1b_scatter_u32offset_s32() {
    let mut storage = [0 as i8; 1280usize];
    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
    svst1b_scatter_u32offset_s32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i8 || val == i as i8);
    }
    svsetffr();
    let loaded = svld1sb_gather_u32offset_s32(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
    assert_vector_matches_i32(
        loaded,
        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sh_gather_u32offset_s32_with_svst1h_scatter_u32offset_s32() {
    let mut storage = [0 as i16; 640usize];
    let data = svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
    svst1h_scatter_u32offset_s32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i16 || val == i as i16);
    }
    svsetffr();
    let loaded =
        svld1sh_gather_u32offset_s32(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
    assert_vector_matches_i32(
        loaded,
        svindex_s32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sb_gather_u32offset_u32_with_svst1b_scatter_u32offset_u32() {
    let mut storage = [0 as u8; 1280usize];
    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_u32(0, 1u32.try_into().unwrap());
    svst1b_scatter_u32offset_u32(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as u8 || val == i as u8);
    }
    svsetffr();
    let loaded = svld1sb_gather_u32offset_u32(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
    assert_vector_matches_u32(
        loaded,
        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sh_gather_u32offset_u32_with_svst1h_scatter_u32offset_u32() {
    let mut storage = [0 as u16; 640usize];
    let data = svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_u32(0, 2u32.try_into().unwrap());
    svst1h_scatter_u32offset_u32(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as u16 || val == i as u16);
    }
    svsetffr();
    let loaded =
        svld1sh_gather_u32offset_u32(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
    assert_vector_matches_u32(
        loaded,
        svindex_u32((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sb_gather_u64offset_s64_with_svst1b_scatter_u64offset_s64() {
    let mut storage = [0 as i8; 1280usize];
    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
    svst1b_scatter_u64offset_s64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i8 || val == i as i8);
    }
    svsetffr();
    let loaded = svld1sb_gather_u64offset_s64(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
    assert_vector_matches_i64(
        loaded,
        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sh_gather_u64offset_s64_with_svst1h_scatter_u64offset_s64() {
    let mut storage = [0 as i16; 640usize];
    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
    svst1h_scatter_u64offset_s64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i16 || val == i as i16);
    }
    svsetffr();
    let loaded =
        svld1sh_gather_u64offset_s64(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
    assert_vector_matches_i64(
        loaded,
        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sw_gather_u64offset_s64_with_svst1w_scatter_u64offset_s64() {
    let mut storage = [0 as i32; 320usize];
    let data = svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
    svst1w_scatter_u64offset_s64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i32 || val == i as i32);
    }
    svsetffr();
    let loaded =
        svld1sw_gather_u64offset_s64(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
    assert_vector_matches_i64(
        loaded,
        svindex_s64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sb_gather_u64offset_u64_with_svst1b_scatter_u64offset_u64() {
    let mut storage = [0 as u8; 1280usize];
    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
    svst1b_scatter_u64offset_u64(svptrue_b8(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as u8 || val == i as u8);
    }
    svsetffr();
    let loaded = svld1sb_gather_u64offset_u64(svptrue_b8(), storage.as_ptr() as *const i8, offsets);
    assert_vector_matches_u64(
        loaded,
        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sh_gather_u64offset_u64_with_svst1h_scatter_u64offset_u64() {
    let mut storage = [0 as u16; 640usize];
    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
    svst1h_scatter_u64offset_u64(svptrue_b16(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as u16 || val == i as u16);
    }
    svsetffr();
    let loaded =
        svld1sh_gather_u64offset_u64(svptrue_b16(), storage.as_ptr() as *const i16, offsets);
    assert_vector_matches_u64(
        loaded,
        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sw_gather_u64offset_u64_with_svst1w_scatter_u64offset_u64() {
    let mut storage = [0 as u32; 320usize];
    let data = svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let offsets = svindex_u64(0, 4u32.try_into().unwrap());
    svst1w_scatter_u64offset_u64(svptrue_b32(), storage.as_mut_ptr(), offsets, data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as u32 || val == i as u32);
    }
    svsetffr();
    let loaded =
        svld1sw_gather_u64offset_u64(svptrue_b32(), storage.as_ptr() as *const i32, offsets);
    assert_vector_matches_u64(
        loaded,
        svindex_u64((0usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sb_gather_u32base_offset_s32_with_svst1b_scatter_u32base_offset_s32() {
    let mut storage = [0 as i8; 1280usize];
    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let bases = svindex_u32(0, 1u32.try_into().unwrap());
    svst1b_scatter_u32base_offset_s32(
        svptrue_b8(),
        bases,
        storage.as_ptr() as i64 + 1u32 as i64,
        data,
    );
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i8 || val == i as i8);
    }
    svsetffr();
    let loaded = svld1sb_gather_u32base_offset_s32(
        svptrue_b8(),
        bases,
        storage.as_ptr() as i64 + 1u32 as i64,
    );
    assert_vector_matches_i32(
        loaded,
        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sh_gather_u32base_offset_s32_with_svst1h_scatter_u32base_offset_s32() {
    let mut storage = [0 as i16; 640usize];
    let data = svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let bases = svindex_u32(0, 2u32.try_into().unwrap());
    svst1h_scatter_u32base_offset_s32(
        svptrue_b16(),
        bases,
        storage.as_ptr() as i64 + 2u32 as i64,
        data,
    );
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i16 || val == i as i16);
    }
    svsetffr();
    let loaded = svld1sh_gather_u32base_offset_s32(
        svptrue_b16(),
        bases,
        storage.as_ptr() as i64 + 2u32 as i64,
    );
    assert_vector_matches_i32(
        loaded,
        svindex_s32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sb_gather_u32base_offset_u32_with_svst1b_scatter_u32base_offset_u32() {
    let mut storage = [0 as i8; 1280usize];
    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let bases = svindex_u32(0, 1u32.try_into().unwrap());
    svst1b_scatter_u32base_offset_u32(
        svptrue_b8(),
        bases,
        storage.as_ptr() as i64 + 1u32 as i64,
        data,
    );
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i8 || val == i as i8);
    }
    svsetffr();
    let loaded = svld1sb_gather_u32base_offset_u32(
        svptrue_b8(),
        bases,
        storage.as_ptr() as i64 + 1u32 as i64,
    );
    assert_vector_matches_u32(
        loaded,
        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sh_gather_u32base_offset_u32_with_svst1h_scatter_u32base_offset_u32() {
    let mut storage = [0 as i16; 640usize];
    let data = svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let bases = svindex_u32(0, 2u32.try_into().unwrap());
    svst1h_scatter_u32base_offset_u32(
        svptrue_b16(),
        bases,
        storage.as_ptr() as i64 + 2u32 as i64,
        data,
    );
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i16 || val == i as i16);
    }
    svsetffr();
    let loaded = svld1sh_gather_u32base_offset_u32(
        svptrue_b16(),
        bases,
        storage.as_ptr() as i64 + 2u32 as i64,
    );
    assert_vector_matches_u32(
        loaded,
        svindex_u32((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sb_gather_u64base_offset_s64_with_svst1b_scatter_u64base_offset_s64() {
    let mut storage = [0 as i8; 1280usize];
    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let bases = svdup_n_u64(storage.as_ptr() as u64);
    let offsets = svindex_u64(0, 1u32.try_into().unwrap());
    let bases = svadd_u64_x(svptrue_b8(), bases, offsets);
    svst1b_scatter_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap(), data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i8 || val == i as i8);
    }
    svsetffr();
    let loaded = svld1sb_gather_u64base_offset_s64(svptrue_b8(), bases, 1u32.try_into().unwrap());
    assert_vector_matches_i64(
        loaded,
        svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap()),
    );
}
#[simd_test(enable = "sve")]
unsafe fn test_svld1sh_gather_u64base_offset_s64_with_svst1h_scatter_u64base_offset_s64() {
    let mut storage = [0 as i16; 640usize];
    let data = svindex_s64((1usize).try_into().unwrap(), 1usize.try_into().unwrap());
    let bases = svdup_n_u64(storage.as_ptr() as u64);
    let offsets = svindex_u64(0, 2u32.try_into().unwrap());
    let bases = svadd_u64_x(svptrue_b16(), bases, offsets);
    svst1h_scatter_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap(), data);
    for (i, &val) in storage.iter().enumerate() {
        assert!(val == 0 as i16 || val == i as i16);
    }
    svsetffr();
    let loaded = svld1sh_gather_u64base_offset_s64(svptrue_b16(), bases, 2u32.try_into().unwrap());
---
    x12: bool,
    x13: bool,
    x14: bool,
    x15: bool,
) -> svbool_t {
    let op1 = svdupq_n_s8(
        x0 as i8, x1 as i8, x2 as i8, x3 as i8, x4 as i8, x5 as i8, x6 as i8, x7 as i8, x8 as i8,
        x9 as i8, x10 as i8, x11 as i8, x12 as i8, x13 as i8, x14 as i8, x15 as i8,
    );
    svcmpne_wide_s8(svptrue_b8(), op1, svdup_n_s64(0))
}
#[doc = "Broadcast a quadword of scalars"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_f32)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
pub fn svdupq_n_f32(x0: f32, x1: f32, x2: f32, x3: f32) -> svfloat32_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            target_arch = "aarch64",
            link_name = "llvm.vector.insert.nxv4f32.v4f32"
        )]
        fn _svdupq_n_f32(op0: svfloat32_t, op1: float32x4_t, idx: i64) -> svfloat32_t;
    }
    unsafe {
        let op = _svdupq_n_f32(svundef_f32(), crate::mem::transmute([x0, x1, x2, x3]), 0);
        svdupq_lane_f32(op, 0)
    }
}
#[doc = "Broadcast a quadword of scalars"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s32)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
pub fn svdupq_n_s32(x0: i32, x1: i32, x2: i32, x3: i32) -> svint32_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            target_arch = "aarch64",
            link_name = "llvm.vector.insert.nxv4i32.v4i32"
        )]
        fn _svdupq_n_s32(op0: svint32_t, op1: int32x4_t, idx: i64) -> svint32_t;
    }
    unsafe {
        let op = _svdupq_n_s32(svundef_s32(), crate::mem::transmute([x0, x1, x2, x3]), 0);
        svdupq_lane_s32(op, 0)
    }
}
#[doc = "Broadcast a quadword of scalars"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u32)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
pub fn svdupq_n_u32(x0: u32, x1: u32, x2: u32, x3: u32) -> svuint32_t {
    unsafe {
        svdupq_n_s32(
            x0.as_signed(),
            x1.as_signed(),
            x2.as_signed(),
            x3.as_signed(),
        )
        .as_unsigned()
    }
}
#[doc = "Broadcast a quadword of scalars"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_f64)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
pub fn svdupq_n_f64(x0: f64, x1: f64) -> svfloat64_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            target_arch = "aarch64",
            link_name = "llvm.vector.insert.nxv2f64.v2f64"
        )]
        fn _svdupq_n_f64(op0: svfloat64_t, op1: float64x2_t, idx: i64) -> svfloat64_t;
    }
    unsafe {
        let op = _svdupq_n_f64(svundef_f64(), crate::mem::transmute([x0, x1]), 0);
        svdupq_lane_f64(op, 0)
    }
}
#[doc = "Broadcast a quadword of scalars"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s64)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
pub fn svdupq_n_s64(x0: i64, x1: i64) -> svint64_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            target_arch = "aarch64",
            link_name = "llvm.vector.insert.nxv2i64.v2i64"
        )]
        fn _svdupq_n_s64(op0: svint64_t, op1: int64x2_t, idx: i64) -> svint64_t;
    }
    unsafe {
        let op = _svdupq_n_s64(svundef_s64(), crate::mem::transmute([x0, x1]), 0);
        svdupq_lane_s64(op, 0)
    }
}
#[doc = "Broadcast a quadword of scalars"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u64)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
pub fn svdupq_n_u64(x0: u64, x1: u64) -> svuint64_t {
    unsafe { svdupq_n_s64(x0.as_signed(), x1.as_signed()).as_unsigned() }
}
#[doc = "Broadcast a quadword of scalars"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s16)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
pub fn svdupq_n_s16(
    x0: i16,
    x1: i16,
    x2: i16,
    x3: i16,
    x4: i16,
    x5: i16,
    x6: i16,
    x7: i16,
) -> svint16_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            target_arch = "aarch64",
            link_name = "llvm.vector.insert.nxv8i16.v8i16"
        )]
        fn _svdupq_n_s16(op0: svint16_t, op1: int16x8_t, idx: i64) -> svint16_t;
    }
    unsafe {
        let op = _svdupq_n_s16(
            svundef_s16(),
            crate::mem::transmute([x0, x1, x2, x3, x4, x5, x6, x7]),
            0,
        );
        svdupq_lane_s16(op, 0)
    }
}
#[doc = "Broadcast a quadword of scalars"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u16)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
pub fn svdupq_n_u16(
    x0: u16,
    x1: u16,
    x2: u16,
    x3: u16,
    x4: u16,
    x5: u16,
    x6: u16,
    x7: u16,
) -> svuint16_t {
    unsafe {
        svdupq_n_s16(
            x0.as_signed(),
            x1.as_signed(),
            x2.as_signed(),
            x3.as_signed(),
            x4.as_signed(),
            x5.as_signed(),
            x6.as_signed(),
            x7.as_signed(),
        )
        .as_unsigned()
    }
}
#[doc = "Broadcast a quadword of scalars"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_s8)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
pub fn svdupq_n_s8(
    x0: i8,
    x1: i8,
    x2: i8,
    x3: i8,
    x4: i8,
---
) -> svint8_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(
            target_arch = "aarch64",
            link_name = "llvm.vector.insert.nxv16i8.v16i8"
        )]
        fn _svdupq_n_s8(op0: svint8_t, op1: int8x16_t, idx: i64) -> svint8_t;
    }
    unsafe {
        let op = _svdupq_n_s8(
            svundef_s8(),
            crate::mem::transmute([
                x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, x14, x15,
            ]),
            0,
        );
        svdupq_lane_s8(op, 0)
    }
}
#[doc = "Broadcast a quadword of scalars"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/svdupq[_n]_u8)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
pub fn svdupq_n_u8(
    x0: u8,
    x1: u8,
    x2: u8,
    x3: u8,
    x4: u8,
---
    x12: u8,
    x13: u8,
    x14: u8,
    x15: u8,
) -> svuint8_t {
    unsafe {
        svdupq_n_s8(
            x0.as_signed(),
            x1.as_signed(),
            x2.as_signed(),
            x3.as_signed(),
            x4.as_signed(),
            x5.as_signed(),
            x6.as_signed(),
            x7.as_signed(),
            x8.as_signed(),
            x9.as_signed(),
            x10.as_signed(),
            x11.as_signed(),
            x12.as_signed(),
            x13.as_signed(),
            x14.as_signed(),
            x15.as_signed(),
        )
        .as_unsigned()
    }
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_b]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.z.nvx16i1")]
        fn _sveor_b_z(pg: svbool_t, op1: svbool_t, op2: svbool_t) -> svbool_t;
    }
    unsafe { _sveor_b_z(pg, op1, op2) }
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv16i8")]
        fn _sveor_s8_m(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t;
    }
    unsafe { _sveor_s8_m(pg, op1, op2) }
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_s8_m(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
    sveor_s8_m(pg, op1, svdup_n_s8(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_s8_x(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
    sveor_s8_m(pg, op1, op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_s8_x(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
    sveor_s8_x(pg, op1, svdup_n_s8(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s8]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_s8_z(pg: svbool_t, op1: svint8_t, op2: svint8_t) -> svint8_t {
    sveor_s8_m(pg, svsel_s8(pg, op1, svdup_n_s8(0)), op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s8]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_s8_z(pg: svbool_t, op1: svint8_t, op2: i8) -> svint8_t {
    sveor_s8_z(pg, op1, svdup_n_s8(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_s16_m(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv8i16")]
        fn _sveor_s16_m(pg: svbool8_t, op1: svint16_t, op2: svint16_t) -> svint16_t;
    }
    unsafe { _sveor_s16_m(pg.sve_into(), op1, op2) }
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_s16_m(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
    sveor_s16_m(pg, op1, svdup_n_s16(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_s16_x(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
    sveor_s16_m(pg, op1, op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_s16_x(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
    sveor_s16_x(pg, op1, svdup_n_s16(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s16]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_s16_z(pg: svbool_t, op1: svint16_t, op2: svint16_t) -> svint16_t {
    sveor_s16_m(pg, svsel_s16(pg, op1, svdup_n_s16(0)), op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s16]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_s16_z(pg: svbool_t, op1: svint16_t, op2: i16) -> svint16_t {
    sveor_s16_z(pg, op1, svdup_n_s16(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_s32_m(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv4i32")]
        fn _sveor_s32_m(pg: svbool4_t, op1: svint32_t, op2: svint32_t) -> svint32_t;
    }
    unsafe { _sveor_s32_m(pg.sve_into(), op1, op2) }
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_s32_m(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
    sveor_s32_m(pg, op1, svdup_n_s32(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_s32_x(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
    sveor_s32_m(pg, op1, op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_s32_x(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
    sveor_s32_x(pg, op1, svdup_n_s32(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s32]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_s32_z(pg: svbool_t, op1: svint32_t, op2: svint32_t) -> svint32_t {
    sveor_s32_m(pg, svsel_s32(pg, op1, svdup_n_s32(0)), op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s32]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_s32_z(pg: svbool_t, op1: svint32_t, op2: i32) -> svint32_t {
    sveor_s32_z(pg, op1, svdup_n_s32(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_s64_m(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eor.nxv2i64")]
        fn _sveor_s64_m(pg: svbool2_t, op1: svint64_t, op2: svint64_t) -> svint64_t;
    }
    unsafe { _sveor_s64_m(pg.sve_into(), op1, op2) }
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_s64_m(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
    sveor_s64_m(pg, op1, svdup_n_s64(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_s64_x(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
    sveor_s64_m(pg, op1, op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_s64_x(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
    sveor_s64_x(pg, op1, svdup_n_s64(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_s64]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_s64_z(pg: svbool_t, op1: svint64_t, op2: svint64_t) -> svint64_t {
    sveor_s64_m(pg, svsel_s64(pg, op1, svdup_n_s64(0)), op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_s64]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_s64_z(pg: svbool_t, op1: svint64_t, op2: i64) -> svint64_t {
    sveor_s64_z(pg, op1, svdup_n_s64(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_u8_m(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
    unsafe { sveor_s8_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_u8_m(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
    sveor_u8_m(pg, op1, svdup_n_u8(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_u8_x(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
    sveor_u8_m(pg, op1, op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_u8_x(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
    sveor_u8_x(pg, op1, svdup_n_u8(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u8]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_u8_z(pg: svbool_t, op1: svuint8_t, op2: svuint8_t) -> svuint8_t {
    sveor_u8_m(pg, svsel_u8(pg, op1, svdup_n_u8(0)), op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u8]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_u8_z(pg: svbool_t, op1: svuint8_t, op2: u8) -> svuint8_t {
    sveor_u8_z(pg, op1, svdup_n_u8(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_u16_m(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
    unsafe { sveor_s16_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_u16_m(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
    sveor_u16_m(pg, op1, svdup_n_u16(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_u16_x(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
    sveor_u16_m(pg, op1, op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_u16_x(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
    sveor_u16_x(pg, op1, svdup_n_u16(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u16]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_u16_z(pg: svbool_t, op1: svuint16_t, op2: svuint16_t) -> svuint16_t {
    sveor_u16_m(pg, svsel_u16(pg, op1, svdup_n_u16(0)), op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u16]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_u16_z(pg: svbool_t, op1: svuint16_t, op2: u16) -> svuint16_t {
    sveor_u16_z(pg, op1, svdup_n_u16(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_u32_m(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
    unsafe { sveor_s32_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_u32_m(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
    sveor_u32_m(pg, op1, svdup_n_u32(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_u32_x(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
    sveor_u32_m(pg, op1, op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_u32_x(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
    sveor_u32_x(pg, op1, svdup_n_u32(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u32]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_u32_z(pg: svbool_t, op1: svuint32_t, op2: svuint32_t) -> svuint32_t {
    sveor_u32_m(pg, svsel_u32(pg, op1, svdup_n_u32(0)), op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u32]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_u32_z(pg: svbool_t, op1: svuint32_t, op2: u32) -> svuint32_t {
    sveor_u32_z(pg, op1, svdup_n_u32(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_u64_m(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
    unsafe { sveor_s64_m(pg, op1.as_signed(), op2.as_signed()).as_unsigned() }
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_m)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_u64_m(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
    sveor_u64_m(pg, op1, svdup_n_u64(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_u64_x(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
    sveor_u64_m(pg, op1, op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_x)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_u64_x(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
    sveor_u64_x(pg, op1, svdup_n_u64(op2))
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_u64]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_u64_z(pg: svbool_t, op1: svuint64_t, op2: svuint64_t) -> svuint64_t {
    sveor_u64_m(pg, svsel_u64(pg, op1, svdup_n_u64(0)), op2)
}
#[doc = "Bitwise exclusive OR"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveor[_n_u64]_z)"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eor))]
pub fn sveor_n_u64_z(pg: svbool_t, op1: svuint64_t, op2: u64) -> svuint64_t {
    sveor_u64_z(pg, op1, svdup_n_u64(op2))
}
#[doc = "Bitwise exclusive OR reduction to scalar"]
#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/sveorv[_s8])"]
#[inline]
#[target_feature(enable = "sve")]
#[unstable(feature = "stdarch_aarch64_sve", issue = "145052")]
#[cfg_attr(test, assert_instr(eorv))]
pub fn sveorv_s8(pg: svbool_t, op: svint8_t) -> i8 {
    unsafe extern "unadjusted" {
        #[cfg_attr(target_arch = "aarch64", link_name = "llvm.aarch64.sve.eorv.nxv16i8")]
        fn _sveorv_s8(pg: svbool_t, op: svint8_t) -> i8;
    }
    unsafe { _sveorv_s8(pg, op) }
---
    Finished `release` profile [optimized + debuginfo] target(s) in 7.01s
     Running `/checkout/obj/build/stdarch-gen-check/release/stdarch-gen-loongarch crates/stdarch-gen-loongarch/lsx.spec`
Error: Os { code: 30, kind: ReadOnlyFilesystem, message: "Read-only file system" }
Bootstrap failed while executing `--stage 2 test --skip tidy --skip src/tools/rust-analyzer --skip tests --skip coverage-map --skip coverage-run --skip library --skip tidyselftest`
Command `/checkout/obj/build/aarch64-unknown-linux-gnu/stage0/bin/cargo run --bin stdarch-gen-loongarch --release -- crates/stdarch-gen-loongarch/lsx.spec [workdir=/checkout/library/stdarch]` failed with exit code 1
Created at: src/bootstrap/src/core/build_steps/test.rs:967:27
Executed at: src/bootstrap/src/core/build_steps/test.rs:977:17

--- BACKTRACE vvv
   0: std::backtrace_rs::backtrace::libunwind::trace
             at /rustc/ef0fb8a2563200e322fa4419f09f65a63742038c/library/std/src/../../backtrace/src/backtrace/libunwind.rs:117:9
   1: std::backtrace_rs::backtrace::trace_unsynchronized::<<std::backtrace::Backtrace>::create::{closure#0}>
             at /rustc/ef0fb8a2563200e322fa4419f09f65a63742038c/library/std/src/../../backtrace/src/backtrace/mod.rs:66:14
   2: <std::backtrace::Backtrace>::create
             at /rustc/ef0fb8a2563200e322fa4419f09f65a63742038c/library/std/src/backtrace.rs:331:13
   3: <bootstrap::utils::exec::DeferredCommand>::finish_process
             at /checkout/src/bootstrap/src/utils/exec.rs:939:17
   4: <bootstrap::utils::exec::DeferredCommand>::wait_for_output::<&bootstrap::utils::exec::ExecutionContext>
             at /checkout/src/bootstrap/src/utils/exec.rs:831:21
   5: <bootstrap::utils::exec::ExecutionContext>::run
             at /checkout/src/bootstrap/src/utils/exec.rs:741:45
   6: <bootstrap::utils::exec::BootstrapCommand>::run::<&bootstrap::core::builder::Builder>
             at /checkout/src/bootstrap/src/utils/exec.rs:339:27
   7: <bootstrap::core::build_steps::test::StdarchGenCheck as bootstrap::core::builder::Step>::run
             at /checkout/src/bootstrap/src/core/build_steps/test.rs:977:17
   8: <bootstrap::core::builder::Builder>::ensure::<bootstrap::core::build_steps::test::StdarchGenCheck>
             at /checkout/src/bootstrap/src/core/builder/mod.rs:1596:36
   9: <bootstrap::core::build_steps::test::StdarchGenCheck as bootstrap::core::builder::Step>::make_run
             at /checkout/src/bootstrap/src/core/build_steps/test.rs:929:21
  10: <bootstrap::core::builder::StepDescription>::maybe_run
             at /checkout/src/bootstrap/src/core/builder/mod.rs:476:13
  11: bootstrap::core::builder::cli_paths::match_paths_to_steps_and_run
             at /checkout/src/bootstrap/src/core/builder/cli_paths.rs:141:22
  12: <bootstrap::core::builder::Builder>::run_step_descriptions
             at /checkout/src/bootstrap/src/core/builder/mod.rs:1139:9
  13: <bootstrap::core::builder::Builder>::execute_cli
             at /checkout/src/bootstrap/src/core/builder/mod.rs:1118:14
  14: <bootstrap::Build>::build
             at /checkout/src/bootstrap/src/lib.rs:803:25
  15: bootstrap::main
             at /checkout/src/bootstrap/src/bin/main.rs:130:11
  16: <fn() as core::ops::function::FnOnce<()>>::call_once
             at /rustc/ef0fb8a2563200e322fa4419f09f65a63742038c/library/core/src/ops/function.rs:250:5
  17: std::sys::backtrace::__rust_begin_short_backtrace::<fn(), ()>
             at /rustc/ef0fb8a2563200e322fa4419f09f65a63742038c/library/std/src/sys/backtrace.rs:166:18
  18: std::rt::lang_start::<()>::{closure#0}
             at /rustc/ef0fb8a2563200e322fa4419f09f65a63742038c/library/std/src/rt.rs:206:18
  19: <&dyn core::ops::function::Fn<(), Output = i32> + core::panic::unwind_safe::RefUnwindSafe + core::marker::Sync as core::ops::function::FnOnce<()>>::call_once
             at /rustc/ef0fb8a2563200e322fa4419f09f65a63742038c/library/core/src/ops/function.rs:287:21
  20: std::panicking::catch_unwind::do_call::<&dyn core::ops::function::Fn<(), Output = i32> + core::panic::unwind_safe::RefUnwindSafe + core::marker::Sync, i32>
             at /rustc/ef0fb8a2563200e322fa4419f09f65a63742038c/library/std/src/panicking.rs:581:40
  21: std::panicking::catch_unwind::<i32, &dyn core::ops::function::Fn<(), Output = i32> + core::panic::unwind_safe::RefUnwindSafe + core::marker::Sync>
             at /rustc/ef0fb8a2563200e322fa4419f09f65a63742038c/library/std/src/panicking.rs:544:19
  22: std::panic::catch_unwind::<&dyn core::ops::function::Fn<(), Output = i32> + core::panic::unwind_safe::RefUnwindSafe + core::marker::Sync, i32>
             at /rustc/ef0fb8a2563200e322fa4419f09f65a63742038c/library/std/src/panic.rs:359:14
  23: std::rt::lang_start_internal::{closure#0}
             at /rustc/ef0fb8a2563200e322fa4419f09f65a63742038c/library/std/src/rt.rs:175:24
  24: std::panicking::catch_unwind::do_call::<std::rt::lang_start_internal::{closure#0}, isize>
             at /rustc/ef0fb8a2563200e322fa4419f09f65a63742038c/library/std/src/panicking.rs:581:40
---
  31: __libc_start_main
  32: _start


Command has failed. Rerun with -v to see more details.
Build completed unsuccessfully in 0:35:55
  local time: Mon May 18 07:57:34 UTC 2026
  network time: Mon, 18 May 2026 07:57:34 GMT
##[error]Process completed with exit code 1.
##[group]Run echo "disk usage:"

port stdarch-gen checks into bootstrap

775ac40

rustbot assigned Kobzol May 17, 2026

rustbot added A-testsuite Area: The testsuite used to check the correctness of rustc S-waiting-on-review Status: Awaiting review from the assignee but also interested parties. T-bootstrap Relevant to the bootstrap subteam: Rust's build system (x.py and src/bootstrap) labels May 17, 2026

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fix: set CARGO_TARGET_DIR for read-only CI

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bootstrap: add bootstrap step to run stdarch-gen checks in CI#156674

bootstrap: add bootstrap step to run stdarch-gen checks in CI#156674
xonx4l wants to merge 3 commits into
rust-lang:mainfrom
xonx4l:port-stdarch-gen

xonx4l commented May 17, 2026

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xonx4l commented May 17, 2026

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