Advanced Matrix Extensions (AMX) Guide
UME::SIMD A library for explicit simd vectorization.
Kite: Architecture Simulator for RISC-V Instruction Set
My very own CPU architecture! Emulator availible!
An assembler and hardware simulator for the Mano Basic Computer, a 16 bit computer
RISCAL is a 32-bit reduced instruction-set computer (RISC) designed for learning and research purposes. It is named after my dog, Rascal.
This repository contains a fully working GCC cross-compiler toolchain targeting the RISC-V architecture, along with a detailed research paper that provides an overview of Instruction Set Architectures (ISAs), the role of compilers, and the RISC-V compilation flow.
Intrinsics are high level functions implemented in C language and are based in some ISAs. The mainly purpose is simulate these architectures in SiNUCA (Simulator of Non-Uniforme Caches)..
Create and represent instruction sets in code easily.
C++ basic instruction set simulator
SRP16 is free and open ISA for 16-bit CPUs and Microcontrollers.
Repository for the CENG513 Course that I have taken at IZTECH
C++26 Custom Instruction Set Architecture Framework
ISA Simulator emulates basic ISA operations, managing memory, registers, and instruction execution
We develop a physical computer programming language using Arduino microcontroller board.
TXT-8 is a simple 8-bit text-based virtual machine with the intent of education on virtualization.
Simulate a 5 stage - Instrcuton Fetch | Decode | Execute | Memory | Write back Simple processor with Instruction Level Parallelism (ILP) including buffers, handling data and control hazards by stalling.
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